Memory system, memory controller and operating method thereof

ABSTRACT

A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to KoreanPatent Application No, 10-2019-0123643, filed in the Korean IntellectualProperty Office on Oct. 7, 2019, which is incorporated herein byreference in its entirety.

BACKGROUND 1. Technical Field

Various embodiments generally relate to a memory system, a memorycontroller and an operating method.

2. Related Art

A memory system operating as a storage device stores data based on arequest of a host, such as a computer, a mobile terminal such as asmartphone or a tablet, or any of various other electronic devices. Thememory system may be of a type which stores data in a magnetic disk,such as a hard disk drive (HDD), or a type which stores data in anonvolatile memory, such as a solid state drive (SDD), a universal flashstorage (UFS) device or an embedded MMC (eMMC) device.

The memory system may further include a memory controller forcontrolling a memory device. The memory controller may receive a commandfrom the host, and may perform or control an operation for reading,writing or erasing data with respect to a volatile memory or anonvolatile memory in the memory system, based on the received command.The memory controller may drive firmware for performing logicalcalculations to execute or control these operations.

The memory controller drives the firmware for performing theabove-described logical calculations, through a processor therein. Theprocessor may be a multi-core processor including a plurality of coreswhich operate in parallel.

SUMMARY

Various embodiments are directed to a memory system, a memory controllerand an operating method, capable of writing data in a specific unit in amemory system using a multi-core.

Also, various embodiments are directed to a memory system, a memorycontroller and an operating method, capable of ensuring that data iswritten while its atomicity is maintained when an SPO occurs in a memorysystem using a multi-core.

In one aspect, embodiments of the disclosure may provide a memory systemincluding: a memory device including a plurality of memory areas; and amemory controller configured to control the memory device.

The memory controller may include one main core.

The memory controller may include a plurality of sub-cores whichcommunicate with the main core and control write operations on one ormore memory areas among the plurality of memory areas.

The main core may receive a target command for an operation of writingtarget data to the memory device, from a host.

In response to the target command, the main core may divide the targetdata into data units each having a size equal to or less than athreshold size, and may allocate the data units to the plurality ofsub-cores.

The memory controller may control a first data unit among the data unitssuch that the entire first data unit is written to the memory device ornone of the first data unit is written to the memory device.

The memory controller may write the first data unit to the plurality ofmemory areas by distributing the first data unit as a plurality ofsub-data units. The main core may divide the first data unit into aplurality of sub-data units and distribute the sub-data unit. Thesub-cores may write the distributed sub-data units to the correspondingmemory areas.

A first sub-core among the plurality of sub-cores may write a firstsub-data unit among the plurality of sub-data units to the correspondingmemory area which is controlled by the first sub-core.

When writing the first sub-data unit to the target memory area, thefirst sub-core may write an identification of the target command and asize value of the first sub-data unit.

The first sub-core may report the identification of the target commandto the main core when an uncorrectable error is detected in a piece ofthe first sub-data unit during a sudden power-off recovery (SPQR)operation.

Based on the identification of the target command reported from thefirst sub-core, the main core may instruct a second sub-core differentfrom the first sub-core among the plurality of sub-cores, to unmap asecond sub-data unit which is written to a memory area controlled by thesecond sub-core, among the plurality of sub-data units.

In another aspect, embodiments of the disclosure may provide a memorycontroller including: a memory interface configured to communicate witha memory device including a plurality of memory areas and a controlcircuit configured to control the memory device.

The control circuit may include one main core.

The control circuit may include a plurality of sub-cores whichcommunicate with the main core and control write operations on one ormore memory areas among the plurality of memory areas.

The main core may receive a target command for an operation of writingtarget data to the memory device, from a host.

In response to the target command, the main core may divide the targetdata into data units each having a size equal to or less than athreshold size, and may allocate the data units to the plurality ofsub-cores.

The control circuit may control a first data unit among the data units,such that the entire first data unit is written to the memory device ornone of the first data unit is written to the memory device.

The control circuit may write the first data unit to the plurality ofmemory areas by distributing the first data unit as a plurality ofsub-data units. The main core may divide the first data unit into aplurality of sub-data units and distribute the sub-data unit. Thesub-cores may write the distributed sub-data units to the correspondingmemory areas.

A first sub-core among the plurality of sub-cores may write a firstsub-data unit among the plurality of sub-data units to a target memoryarea which is controlled by the first sub-core.

When writing the first sub-data unit to the target memory area, thefirst sub-core may write an identification of the target command and asize value of the first sub-data unit.

The first sub-core may report the identification of the target commandto the main core when an uncorrectable error is detected in a piece ofthe first sub-data unit during a sudden power-off recovery (SPQR)operation.

Based on the identification of the target command reported from thefirst sub-core, the main core may instruct a second sub-core differentfrom the first sub-core among the plurality of sub-cores, to unmap asecond sub-data unit which is written to a memory area controlled by thesecond sub-core, among the plurality of sub-data units.

In still another aspect, embodiments of the disclosure may provide amethod for operating a memory controller including one main core and aplurality of sub-cores.

The plurality of sub-cores may communicate with the main core, and maycontrol data write operations for some among a plurality of memoryareas.

The method for operating a memory controller may include receiving, bythe main core, a target command from a host. The target command may be acommand for an operation of writing target data to a memory device.

The method for operating a memory controller may include dividing, bythe main core, the target data into data units each having a size equalto or less than a threshold size and allocating, by the main core, thedata units to the plurality of sub-cores.

The method for operating a memory controller may include controlling, bythe sub-cores, a first data unit among the data units, such that theentire first data unit is written to the memory device or none of thefirst data unit is written to the memory device.

In one aspect, embodiments of the disclosure may provide a memory systemincluding: first and second memory areas; a main controller configuredto divide a write data unit into at least first and second sub-dataunits; and first and second sub-controllers configured to control thefirst and second memory areas to store therein the first and secondsub-data units respectively.

Each of the first and second sub-controllers may be further configuredto control the corresponding first or second memory area to storetherein, along with the corresponding first or second sub-data unit,identification of the write data unit.

The first sub-controller may be further configured to report, when anerror in the first sub-data unit is detected during a sudden power offrecovery operation, the identification to the second sub-controller.

The second sub-controller may be further configured to unmap, during thesudden power off recovery operation, the second sub-data unit based onthe reported identification, thereby maintaining atomicy of the writedata unit.

According to embodiments of the disclosure, it is possible to write datain a specific unit in a memory system using a multi-core.

Also, according to embodiments of the disclosure, it is possible toensure that data is written while its atomicity is maintained when anSPO occurs in a memory system using a multi-core.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a configuration of a memorysystem in accordance with an embodiment of the disclosure.

FIG. 2 is a block diagram schematically illustrating a memory device inaccordance with an embodiment of the disclosure.

FIG. 3 is a diagram schematically illustrating a representative memoryblock of the memory device in accordance with an embodiment of thedisclosure.

FIG. 4 is a diagram illustrating word lines and bit lines of the memorydevice in accordance with an embodiment of the disclosure.

FIG. 5 is a diagram illustrating a structure of a main core andsub-cores in the memory system in accordance with an icy embodiment ofthe disclosure.

FIG. 6 is a diagram illustrating an operation of writing a data unit inthe memory system in accordance with an embodiment of the disclosure.

FIG. 7 is a diagram illustrating an operation in which a data unit isfurther divided into sub-data units that are distributed and written tothe memory device in accordance with an embodiment of the disclosure.

FIG. 8 is a diagram illustrating an operation of writing sub-data unitsto the memory device in the memory system in accordance with anembodiment of the disclosure,

FIG. 9 is a diagram illustrating an operation of writing a sub-data unitto memory areas in the memory device in the memory system in accordancewith an embodiment of the disclosure.

FIG. 10 is a diagram illustrating an operation of writing a sub-dataunit to memory areas in the memory device in the memory system inaccordance with an embodiment of the disclosure.

FIG. 11 is a diagram illustrating a sudden power-off recovery (SPOR)operation in the memory system in accordance with an embodiment of thedisclosure.

FIGS. 12 to 14 are diagrams illustrating an operation when anuncorrectable error correction code (UECC) is detected during a SPORoperation in the memory system in accordance with an embodiment of thedisclosure.

FIG. 15 is a flow chart to assist in the explanation of a SPOR operationin the memory system in accordance with an embodiment of the disclosure.

FIG. 16 is a flow chart to assist in the explanation of a method foroperating a memory controller in accordance with an embodiment of thedisclosure.

FIG. 17 is a schematic diagram illustrating a configuration of acomputing system in accordance with an embodiment of the disclosure.

DETAILED DESCRIPTION

Various embodiments of the disclosure are described in detail below withreference to the accompanying drawings. Throughout the specification,reference to “an embodiment,” “another embodiment” or the like is notnecessarily to only one embodiment, and different references to any suchphrase are not necessarily to the same embodiment(s). Similarly, theindefinite articles “a” and “an” mean one or more, unless statedotherwise or it is clear from the context that only one is intended.

FIG. 1 is a diagram schematically illustrating a configuration of amemory system 100 in accordance with an embodiment of the disclosure.

Referring to FIG. 1, the memory system 100 may include a memory device110 which stores data, and a memory controller 120 which controls thememory device 110.

The memory device 110 includes a plurality of memory blocks, andoperates in response to the control of the memory controller 120.Operations of the memory device 110 may include, for example, a readoperation, a program operation (also referred to as a write operation)and an erase operation.

The memory device 110 may include a memory cell array including aplurality of memory cells (also simply referred to as “cells”) whichstore data. Such a memory cell array may be disposed in memory blocks.

For example, the memory device 110 may be realized as any of varioustypes such as a DDR SDRAM (double data rate synchronous dynamic randomaccess memory), an LPDDR4 (low power double data rate 4) SDRAM, a GDDR(graphics double data rate) SDRAM, an LPDDR (low power DDR), an RDRAM(Rambus dynamic random access memory), a NAND flash memory, a 3D NANDflash memory, a NOR flash memory, a resistive random access memory(RRAM), a phase-change memory (PRAM), a magnetoresistive random accessmemory (MRAM), a ferroelectric random access memory (FRAM) and/or a spintransfer torque random access memory (STT-RAM).

The memory device 110 may be realized in a three-dimensional arraystructure. Embodiments of the disclosure may be applied to not only aflash memory device in which a charge storage layer is configured by aconductive floating gate but also a charge icy trap flash (CTF) in whicha charge storage layer is configured by a dielectric layer.

The memory device 110 is configured to receive a command, an address andthe like from the memory controller 120 and access a region in thememory cell array which is selected by the address. In other words, thememory device 110 may perform an operation corresponding to the commandfor a region selected by the address.

For example, the memory device 110 may perform a program operation, aread operation and an erase operation. In the program operation, thememory device 110 may program data in a region selected by the address.In the read operation, the memory device 110 may read data from a regionselected by the address. In the erase operation, the memory device 110may erase data stored in a region selected by the address.

The memory controller 120 may control write (program), read, erase andbackground operations for the memory device 110. For example, thebackground operation may include at least one among a garbage collection(GC) operation, a wear leveling (WL) operation, a bad block management(BBM) operation, and the like.

The memory controller 120 may control the operation of the memory device110 according to a request of a host. The memory controller 120 may alsocontrol the operation of the memory device 110 even in the absence of arequest of the host.

The memory controller 120 and the host may be separate components.Alternatively, the memory controller 120 and the host may be integratedinto a single device. By way of example, the following description isgiven in the context of the memory controller 120 and the host beingseparate components.

Referring to FIG. 1, the memory controller 120 may include a memoryinterface 122 and a control circuit 123, and may further include a hostinterface 121.

The host interface 121 provides an interface for communication with thehost.

When receiving a command from the host, the control circuit 123 mayreceive the command through the host interface 121, and then, mayperform an operation of processing the received command.

The memory interface 122 is coupled with the memory device 110 andthereby provides an interface for communication with the memory device110. That is to say, the memory interface 122 may be configured toprovide the interface between the memory device 110 and the memorycontroller 120 in response to the control of the control circuit 123.

The control circuit 123 performs the general control operations of thememory controller 120, thereby controlling the operations of the memorydevice 110. To this end, for instance, the control circuit 123 mayinclude at least one of a processor 124 and a working memory 125, and asthe case may be, may further include an error detection and correctioncircuit (ECC circuit) 126.

The processor 124 may control general operations of the memorycontroller 120, and may perform a logic calculation. The processor 124may communicate with the host through the host interface 121, and maycommunicate with the memory device 110 through the memory interface 122.

The processor 124 may perform the function of a flash translation layer(FTL). The processor 124 may translate a logical block address (LBA)provided by the host, into a physical block address (PBA), through theflash translation layer (FTL). The flash translation layer (FTL) mayreceive the logical block address (LBA) and translate the receivedlogical block address (LBA) into the physical block address (PBA), byusing a mapping table.

There are various address mapping methods of the flash translationlayer, depending on a mapping unit. Representative address mappingmethods include a page mapping method, a block mapping method and ahybrid mapping method.

The processor 124 is configured to randomize data received from thehost. For example, the processor 124 may randomize data received fromthe host, by using a randomizing seed. Randomized data as data to bestored is provided to the memory device 110 and is programmed to thememory cell array.

The processor 124 is configured to derandomize data icy received fromthe memory device 110, in a read operation. For example, the processor124 may derandomize data received from the memory device 110, by using aderandomizing seed, Derandomized data may be outputted to the host.

The processor 124 may control the operation of the memory controller 120by executing firmware. In other words, in order to control generaloperations of the memory controller 120 and perform a logic calculation,the processor 124 may execute (drive) firmware loaded to the workingmemory 125 upon booting.

The firmware as a program to be executed in the memory system 100 mayinclude various functional layers.

For example, the firmware may include at least one among a flashtranslation layer (FTL) which performs a translating function between alogical address requested to the memory system 100 from the host and aphysical address of the memory device 110, a host interface layer (HIL)which serves to analyze a command requested to the memory system 100 asa storage device from the host and transfers the command to the flashtranslation layer (FTL), and a flash interface layer (FIL) whichtransfers a command instructed from the flash translation layer (FTL) tothe memory device 110.

For instance, such firmware may be stored in the memory device 110 andthen be loaded to the working memory 125.

The working memory 125 may store a firmware, a program code, a commandand data to drive the memory controller 120. The working memory 125, forexample, as a volatile memory, may include at least one among an SRAM(static RAM), a DRAM (dynamic RAM) and an SDRAM (synchronous DRAM).

The error detection and correction circuit 126 may be configured todetect an error bit in target data and correct the detected error bit,by using an error correction code. Here, the target data may be, forexample, data stored in the working memory 125, data read from thememory device 110, or the like.

The error detection and correction circuit 126 may be realized to decodedata by using an error correction code. The error detection andcorrection circuit 126 may be realized by any of various code decoders.For example, a decoder which performs unsystematic code decoding or adecoder which performs systematic code decoding may be used.

For example, the error detection and correction circuit 126 may detecterror bit(s) for each read data, in the unit of sector. Namely, eachread data may be constituted by a plurality of sectors. A sector maymean a data unit smaller than a page as a read unit of a flash memory.Sectors constituting each read data may be matched with one another bythe medium of an address.

The error detection and correction circuit 126 may calculate a bit errorrate (BER), and may determine whether an error is correctable or not, inthe unit of sector. For example, when a bit error rate (BER) is higherthan a reference value, the error detection and correction circuit 126may determine that a corresponding sector is uncorrectable or a fail. Onthe other hand, when a bit error rate (BER) is lower than the referencevalue, the error detection and correction circuit 126 may determine thata corresponding sector is correctable or a pass.

The error detection and correction circuit 126 may perform an errordetection and correction operation sequentially for all read data. Whena sector included in read data is correctable, the error detection andcorrection circuit 126 may omit an error detection and correctionoperation for a corresponding sector for next read data. If the errordetection and correction operation for all read data is ended in thisway, the error detection and correction circuit 126 may detect a sectorwhich is determined to be uncorrectable to the last. There may be one ormore sectors that are determined to be uncorrectable. The errordetection and correction circuit 126 may transfer information (forexample, address information) on a sector which is determined to beuncorrectable, to the processor 124.

A bus 127 may be configured to provide channels among the components121, 122, 124, 125 and 126 of the memory controller 120. The bus 127 mayinclude, for example, a control bus for transferring various controlsignals, commands and the likes, and a data bus for transferring variousdata.

The above-described components 121, 122, 124, 125 and 126 of the memorycontroller 120 are exemplary. One or more of icy these components may beomitted, and/or two or more of such components may be integrated intoone. Of course, the memory controller 120 may include one or moreadditional components.

The memory device 110 is described in further detail below withreference to FIG. 2.

FIG. 2 is a block diagram schematically illustrating the memory device110 in accordance with an embodiment of the disclosure.

Referring to FIG. 2, the memory device 110 may include a memory cellarray 210, an address decoder 220, a read and write circuit 230, controllogic 240, and a voltage generation circuit 250.

The memory cell array 210 may include a plurality of memory blocks BLK1to BLKz (z is a natural number of 2 or greater).

In the plurality of memory blocks BLK1 to BLKz, a plurality of wordlines WL and a plurality of bit lines BL may be disposed in anintersecting pattern, and a plurality of memory cells (MC) may bearranged at the intersections.

The plurality of memory blocks BLK1 to BLKz may be coupled with theaddress decoder 220 through the plurality of word lines WL. Theplurality of memory blocks BLK1 to BLKz may be coupled with the read andwrite circuit 230 through the plurality of bit lines BL.

Each of the plurality of memory blocks BLK1 to BLKz may include aplurality of memory cells. For example, the plurality of memory cellsmay be nonvolatile memory cells, which have vertical channel structures.

The memory cell array 210 may be configured as a two-dimensionalstructure, or a three-dimensional structure.

Each of the plurality of memory cells included in the memory cell array210 may store at least 1-bit data. For instance, each of the pluralityof memory cells in the memory cell array 210 may be a single level cell(SLC) which stores 1-bit data, a multi-level cell (MLC) which stores2-bit data, a triple level cell (TLC) which stores 3-bit data, or a quadlevel cell (QLC) which stores 4-bit data. In another embodiment, thememory cell array 210 may include a plurality of memory cells, each ofwhich stores 5 or more-bit data.

Referring to FIG. 2, the address decoder 220, the read and write circuit230, the control logic 240 and the voltage generation circuit 250 mayoperate as peripheral circuits which drive the memory cell array 210.

The address decoder 220 may be coupled to the memory cell array 210through the plurality of word lines WL.

The address decoder 220 may be configured to operate in response to thecontrol of the control logic 240.

The address decoder 220 may receive an address through an input/outputbuffer in the memory device 110. The address decoder 220 may beconfigured to decode a block address in the received address. Theaddress decoder 220 may select at least one memory block depending onthe decoded block address.

The address decoder 220 may receive a read voltage Vread and a passvoltage Vpass from the voltage generation circuit 250.

The address decoder 220 may apply the read voltage Vread to a selectedword line WL in a selected memory block in a read voltage applyingoperation during a read operation, and may apply the pass voltage Vpassto the remaining unselected word lines WL.

The address decoder 220 may apply a verify voltage generated in thevoltage generation circuit 250 to a selected word line WL in a selectedmemory block in a program verify operation, and may apply the passvoltage Vpass to the remaining unselected word lines WL.

The address decoder 220 may be configured to decode a column address inthe received address. The address decoder 220 may transmit the decodedcolumn address to the read and write circuit 230.

A read operation and a program operation of the memory device 110 may beperformed in the unit of page. An address received when a read operationor a program operation is requested may include at least one among ablock address, a row address and a column address.

The address decoder 220 may select one memory block and one word linedepending on a block address and a row address. A column address may bedecoded by the address decoder 220 and be provided to the read and writecircuit 230.

The address decoder 220 may include at least one among a block decoder,a row decoder, a column decoder and an address buffer.

The read and write circuit 230 may include a plurality of page buffersPB. The read and write circuit 230 may operate as a read circuit in aread operation of the memory cell array 210, and may operate as a writecircuit in a write operation of the memory cell array 210.

The read and write circuit 230 described above may also be referred toas a page buffer circuit or a data register circuit which includes aplurality of page buffers PB. The read and write circuit 230 may includedata buffers which operate in a data processing function, and as thecase may be, may further include cache buffers which perform a cachingfunction.

The plurality of page buffers PB may be coupled to the memory cell array210 through the plurality of bit lines BL. The plurality of page buffersPB may continuously supply sensing current to bit lines BL coupled withmemory cells to sense threshold voltages (Vth) of the memory cells in aread operation and a program verify operation, and may latch sensingdata by sensing, through sensing nodes, that the amounts of currentflowing depending on the programmed states of the corresponding memorycells are changed.

The read and write circuit 230 may operate in response to page buffercontrol signals outputted from the control logic 240.

In a read operation, the read and write circuit 230 temporarily storesread data by sensing data of memory cells, and then, outputs data DATAto the input/output buffer of the memory device 110. In an embodiment,the read and write circuit 230 may include a column select circuit inaddition to the page buffers PB or the page registers.

The control logic 240 may be coupled with the address decoder 220, theread and write circuit 230 and the voltage generation circuit 250. Thecontrol logic 240 may receive a command CMD and a control signal CTRLthrough the input/output buffer of the memory device 110.

The control logic 240 may be configured to control general operations ofthe memory device 110 in response to the control signal CTRL. Thecontrol logic 240 may output control signals for adjusting the prechargepotential levels of the sensing nodes of the plurality of page buffersPB.

The control logic 240 may control the read and write circuit 230 toperform a read operation of the memory cell array 210. The voltagegeneration circuit 250 may generate the read voltage Vread and the passvoltage Vpass used in a read operation, in response to a voltagegeneration circuit control signal outputted from the control logic 240.

FIG. 3 is a diagram schematically illustrating a representative memoryblock BLK of the memory device 110 in accordance with an embodiment ofthe disclosure.

Referring to FIG. 3, the memory block BLK in the memory device 110 maybe configured, for example, as a plurality of pages PG and a pluralityof strings STR respectively disposed in different directions such thatthe pages and strings form an intersecting pattern.

The plurality of pages PG correspond to a plurality of word lines WL,and the plurality of strings STR correspond to a plurality of bit linesBL.

In the memory block BLK, the plurality of word lines WL and theplurality of bit lines BL may be disposed to intersect with each other.For example, each of the plurality of word lines WL may be disposed in arow direction, and each of the plurality of bit lines BL may be disposedin a column direction. For another example, each of the plurality ofword lines WL may be disposed in a column direction, and each of theplurality of bit lines BL may be disposed in a row direction.

As the plurality of word lines WL and the plurality of bit lines BLintersect with each other, a plurality of memory cells MC may be definedat such intersections. A transistor TR may be disposed in each memorycell MC.

For example, the transistor TR disposed in each memory cell MC mayinclude a drain, a source and a gate. The drain (or source) of thetransistor TR may be coupled with a corresponding bit line BL directlyor via another transistor TR. The source (or drain) of the transistor TRmay be coupled with a source line (which may be the ground) directly orvia another transistor TR. The gate of the transistor TR may include afloating gate FG which is surrounded by a dielectric and a control gateCG to which a gate voltage is applied from a word line WL.

In each of the plurality of memory blocks BLK1 to BLKz, a first selectline (also referred to as a source select line or a drain select line)may be additionally disposed outside a first outermost word line moreadjacent to the read and write circuit 230, and a second select line(also referred to as a drain select line or a source select line) may beadditionally disposed outside a second outermost word line.

As the case may be, at least one dummy word line may be additionallydisposed between the first outermost word line and the first selectline. At least one dummy word line may also be additionally disposedbetween the second outermost word line and the second select line.

When the memory device 110 has a memory block structure illustrated inFIG. 3, a read operation and a program operation (write operation) maybe performed in the unit of page, and an erase operation may beperformed in the unit of memory block.

FIG. 4 is a diagram illustrating a structure of word lines WL and bitlines BL of the memory device 110 in accordance with an embodiment ofthe disclosure.

Referring to FIG. 4, in the memory device 110, there exist a core areain which memory cells MC are gathered and an auxiliary area whichcorresponds to the remaining area excluding the core area and supportsthe operation of the memory cell array 210.

The core area may be configured by pages PG and strings STR. In such acore area, a plurality of word lines WL1 to WL9 and a plurality of bitlines BL are disposed to intersect with each other.

The plurality of word lines WL1 to WL9 may be coupled with a row decoder410, and the plurality of bit lines BL may be coupled with a columndecoder 420. A data register 430 corresponding to the read and writecircuit 230 may be disposed between the plurality of bit lines BL andthe column decoder 420.

The plurality of word lines WL1 to WL9 correspond to a plurality ofpages PG.

For example, as illustrated in FIG. 4, each of the plurality of wordlines WL1 to WL9 may correspond to one page PG. Alternatively, in thecase in which the size of each of the plurality of word lines WL1 to WL9is large, each of the plurality of word lines WL1 to WL9 may correspondto at least two (for example, two or four) pages PG. Page PG is aminimum unit in performing a program operation and a read operation. Inthe program operation and the read operation, all memory cells MC in thesame page PG may simultaneously perform the corresponding operations.

The plurality of bit lines BL may be coupled with the column decoder 420while being identified as odd-numbered bit lines BL and even-numberedbit lines BL.

In order to access memory cells MC, first, an address may be enteredinto the core area through the row decoder 410 and the column decoder420 via an input/output terminal, and may designate target memory cells.Designating target memory cells means accessing memory cells MCpositioned at sites where the word lines WL1 to WL9 coupled with the rowdecoder 410 and the bit lines BL coupled with the column decoder 420intersect with each other, to program data to the memory cells MC orread out programmed data from the memory cells MC.

A page PG in a first direction (e.g., a horizontal direction asillustrated in FIG. 4) is bound (coupled) by a common line which isreferred to as a word line WL, and a string STR in a second direction(e.g., a vertical direction as illustrated in FIG. 4) is bound (coupled)by a common line which is referred to as a bit line BL. Being bound incommon means that corresponding memory cells MC are structurally coupledwith one another by the same material and also the same voltage issimultaneously applied to the memory cells MC when a voltage is appliedthereto. Of course, as a memory cell MC which is coupled in series andis positioned at an intermediate position or a last position isinfluenced by a voltage drop in a preceding memory cell MC, voltagesapplied to a first memory cell MC and a last memory cell MC may beslightly different from each other.

Since data is programmed and read via the data register 430 in all dataprocessing operations of the memory device 110, the data register 430plays a key role. If data processing of the data register 430 isdelayed, all the other areas need to wait until the data register 430completes the data processing. Also, if the performance of the dataregister 430 is degraded, the overall performance of the memory device110 may be degraded.

Referring to the illustration of FIG. 4, in one string STR, a pluralityof transistors TR1 to TR9 which are coupled with the plurality of wordlines WL1 to WL9 may exist. Areas where the plurality of transistors TR1to TR9 exist correspond to memory cells MC. Each of the plurality oftransistors TR1 to TR9 includes a control gate CG and a floating gate FGas described above.

The plurality of word lines WL1 to WL9 include two outermost word linesWL1 and WL9. A first select line DSL may be additionally disposedoutside a first outermost word line WL1 which is more adjacent to thedata register 430 in terms of signal path, and a second select line SSLmay be additionally disposed outside a second outermost word line WL9.

A first select transistor D-TR which is on-off controlled by the firstselect line DSL has only a gate electrode coupled with the icy firstselect line DSL and does not include a floating gate FG. A second selecttransistor S-TR which is on-off controlled by the second select line SSLhas only a gate electrode coupled with the second select line SSL anddoes not include a floating gate FG.

The first select transistor D-TR serves as a switch which turns on oroff the coupling between a corresponding string STR and the dataregister 430. The second select transistor S-TR serves as a switch whichturns on or off the coupling between the corresponding string STR and asource line SL. That is to say, the first select transistor D-TR and thesecond select transistor S-TR are respectively positioned at oppositeends of the corresponding string STR, and serve as gatekeepers whichcouple and decouple signals.

In a program operation, because it is necessary to fill electrons in atarget memory cell MC of a bit line BL which is to be programmed, thememory system 100 turns on the first select transistor D-TR by applyinga set turn-on voltage Vcc to the gate electrode of the first selecttransistor D-TR, and turns off the second select transistor S-TR byapplying a set turn-off voltage (e.g., 0V) to the gate electrode of thesecond select transistor S-TR.

In a read operation or a verify operation, the memory system 100 turnson both the first select transistor D-TR and the second selecttransistor S-TR. Accordingly, since current may be discharged to thesource line SL corresponding to the ground through the correspondingstring STR, a voltage level of the bit line BL may be measured. However,in the read operation, there may be a time difference between on-offtimings of the first select transistor D-TR and the second selecttransistor S-TR.

In an erase operation, the memory system 100 may supply a set voltage(e.g., +20V) to a substrate through the source line SL. In the eraseoperation, the memory system 100 floats both the first select transistorD-TR and the second select transistor S-TR, thereby providing infiniteresistance. Accordingly, the memory system 100 is structured such thatthe first select transistor D-TR and the second select transistor S-TRdo not function and electrons may operate due to a potential differenceonly between a floating gate FG and the substrate.

FIG. 5 is a diagram illustrating a structure of a main core MC andsub-cores SC in the memory system 100 in accordance with an embodimentof the disclosure.

Referring to FIG. 5, the memory controller 120 of the memory system 100may include one main core MC and a plurality of sub-cores SC.

The main core MC may receive a command from the host, and may transmit aresult of processing the command to the host. The main core MC maycommunicate with the plurality of sub-cores SC, and may controlrespective operations of the plurality of sub-cores SC.

The main core MC may receive a target command from the host. The targetcommand instructs an operation of writing target data to the memorydevice 110.

The memory device 110 may include a plurality of memory areas, eachdenoted by AREA in FIG. 5. Each memory area may be determined in variousways.

For example, the memory device 110 may include a plurality of memorydies, and each memory die may correspond to one memory area.

In this case, each of the plurality of memory dies may include aplurality of memory blocks. Each of the plurality of memory blocks mayinclude a plurality of pages.

As another example, each memory area may represent one or more of aplurality of memory blocks in the memory device 110.

Each of the plurality of sub-cores SC may communicate with the main coreMC, and may control data write (store) operations for one or more of theplurality of memory areas in the memory device 110.

The fact that data is written to a memory area means that data iswritten to a memory die or a memory block in the corresponding memoryarea.

Each sub-core SC may exclusively control one or more memory areas. Thatis, each of the plurality of memory areas in the memory device 110 iscontrolled only by one sub-core SC among the icy plurality of sub-coresSC. That is to say, two or more sub-cores SC do not jointly control onememory area.

Each of the plurality of sub-cores SC may independently control writeoperations for different memory areas. Each of the plurality ofsub-cores SC is not influenced by other sub-cores SC when controlling adata write operation for a memory area controlled by itself.

Each of the plurality of sub-cores SC may communicate with the main coreMC, but the sub-cores SC do not communicate with one another.

The main core MC and the plurality of sub-cores SC may be realized by aplurality of processor cores which are included in the processor 124 inthe memory controller 120.

FIG. 6 is a diagram illustrating an operation of writing a data unit DUin the memory system 100 in accordance with an embodiment of thedisclosure.

Referring to FIG. 6, when receiving, from the host, a target commandTGT_CMD which instructs an operation of writing target data TGT_DATA tothe memory device 110, first, the main core MC in the memory controller120 of the memory system 100 may divide the target data TGT_DATA intodata units DU each having a size equal to or less than a threshold sizeTHR, and may allocate the data units DU to the plurality of sub-coresSC.

For example, if the target data TGT_DATA is 100 KB and the thresholdsize THR is 30 KB, the main core MC of the memory controller 120 maydivide the target data TGT_DATA into three data units each having a sizeof 30 KB and one data unit having a size of 10 KB.

If a size of the target data TGT_DATA is equal to or less than thethreshold size THR, the main core MC of the memory controller 120 mayprocess the target data TGT_DATA as a single data unit.

The memory controller 120 may control the plurality of sub-cores SC towrite a first data unit DU_1 of the data units DU to the memory device110 while maintaining the atomicity of the first data unit DU_1.

The first data unit DU_1 may retain its atomicity when the memorycontroller 120 controls the plurality of sub-cores SC to write all, notpart, of the first data unit DU_1 to or from the memory device 110.

For instance, assume that an SPO (sudden power-off) occurs while thefirst data unit DU_1 is being written to the memory device 110. In thiscase, part of, i.e., a piece of, the first data unit DU_1 may betransiently stored in the memory device 110 at the time of the SPO. Inorder to retain the atomicity of the first data unit DU_1, the memorycontroller 120 may roll back the stored piece of the first data unitDU_1 from the memory device 110 in a recovery operation for the SPO toavoid having only a part of the first data unit DU_1 written to thememory device 110.

In order to roll back the stored piece of the first data unit DU_1 fromthe memory device 110, the memory controller 120 may restore mapinformation between a logical address and a physical address for thestored piece of the first data unit DU_1, to a state before that pieceof the first data unit DU_1 was written to the memory device 110.

As another example of maintaining the atomicity of the first data unitDU_1, the memory controller 120 may write, during the recovery operationfor the SPO, the remaining part of the first data unit DU_1, which hasnot been written to the memory device 110, to the memory device 110, sothat all of first data unit DU_1 is written to the memory device 110.

Hereinafter, a detailed method in which the memory controller 120 writesthe first data unit DU_1 to the memory device 110 while maintainingatomicity of the first data unit DU_1 is described.

FIG. 7 is a diagram illustrating an operation in which a data unit isfurther divided into sub-data units SUB_DU that are distributed andwritten to the memory device 110 in accordance with an embodiment of thedisclosure.

Referring to FIG. 7, as described above, when the main core MC receives,from the host, a target command TGT_CMD which instructs an operation ofwriting target data TGT_DATA to the memory device 110, first, the memorycontroller 120 of the memory system 100 may divide the target dataTGT_DATA into a plurality of data units DU each having a size equal toor less than a threshold size THR.

The memory controller 120 may write a first data unit DU_1, which is oneof the plurality of data units DU, to the plurality of memory areas(each denoted by AREA in FIG. 7) in the memory device 110, bydistributing the first data unit DU_1 to a plurality of sub-data unitsSUB_DU. The main core MC may divide the first data unit DU_1 into aplurality of sub-data units SUB_DU and distribute the sub-data unitsSUB_DU.

Each of the sub-data units SUB_DU may include part of the first dataunit DU_1, and sizes of the respective sub-data units SUB_DU may bedifferent from one another. The respective sub-data units SUB_DU may bewritten to different memory areas AREA.

Each of the plurality of sub-cores SC in the memory controller 120 maybe controlled to write some of the plurality of sub-data units SUB_DU tomemory areas controlled by the corresponding sub-core.

FIG. 8 is a diagram illustrating an operation of writing sub-data unitsSUB_DU to the memory device 110 in the memory system 100 in accordancewith an embodiment of the disclosure.

As described above with reference to FIG. 7, the memory controller 120of the memory system 100 may divide the first data unit DU_1 into theplurality of sub-data units SUB_DU.

A first sub-core SC_1 among the plurality of sub-cores SC in the memorycontroller 120, may write a first sub-data unit SUB_DU_1, among theplurality of sub-data units SUB_DU, to a target memory area, which maybe one of memory areas controlled by the first sub-core SC_1.

The first sub-core SC_1 may write, together with the first sub-data unitSUB_DU_1, identification CID of the target command TGT_CMD and a sizevalue SIZE of the first sub-data unit SUB_DU_1, where CID stands forcommand identification.

The CID of the target command TGT_CMD may be generated by the main coreMC. For example, the main core MC may generate the CID of the targetcommand TGT_CMD by using a separate count value that increases as timegoes by or by using a random numerical value generated by using a factorsuch as a current time, as a seed.

The reason why, in this way, the first sub-core SC_1 writes the CID ofthe target command TGT_CMD and the size value SIZE of the first sub-dataunit SUB_DU_1 together with the first sub-data unit SUB_DU_1 is to allowthe memory controller 120 to control the first data unit DU_1 to bewritten to the memory device 110 while maintaining atomicity of thefirst data unit DU_1.

In a recovery operation after the occurrence of an SPO, in order to keepthe atomicity of the first data unit DU_1, the memory controller 120rolls back a piece of the first data unit DU_1 written to the memorydevice 110 at the time of the SPO, so that this piece of the first dataunit DU_1 returns to a state before written.

To this end, the memory controller 120 may search for data pieces storedin the memory device 110 at the time of the SPO for a sub-data unitSUB_DU of the first data unit DU_1.

The memory controller 120 may detect, based on the CID of the targetcommand TGT_CMD, which is also written at the time of the SPO, thesub-data unit SUB_DU of the first data unit DU_1 among the data piecesstored in the memory device 110 at the time of the SPO.

The memory controller 120 may identify, based on the size value SIZE,which is also written at the time of the SPO, the size of the detectedsub-data unit SUB_DU.

FIG. 9 is a diagram illustrating an operation of writing a sub-data unitSUB_DU to memory areas in the memory device 110 in the memory system 100in accordance with an embodiment of the disclosure.

Referring to FIG. 9, the sub-data unit SUB_DU may be distributed andwritten to pages in one or more memory areas in the memory device 110.Each of the pages in which the distributed sub-data unit SUB_DU isstored may be included in a memory block in any one of the memoryarea(s).

A CID of a target command corresponding to the sub-data unit SUB_DU anda size value SIZE of the sub-data unit SUB_DU may be written to each ofthe plurality of pages in which the distributed sub-data unit SUB_DU isstored.

For example, it is assumed that the CID of the target commandcorresponding to the sub-data unit SUB_DU is 300 and the size value SIZEof the sub-data unit SUB_DU is 12 KB. Further, it is assumed that thedistributed sub-data unit SUB_DU is stored to three pages, i.e., Page1,Page2 and Page3.

In this case, 300 as the CID of the target command corresponding to thesub-data unit SUB_DU and 12 KB as the size value SIZE of the sub-dataunit SUB_DU may be written to each of Page1, Page2 and Page3.

FIG. 10 is a diagram illustrating an operation of writing a sub-dataunit SUB_DU to memory areas in the memory device 110 in the memorysystem 100 in accordance with an embodiment of the disclosure.

Referring to FIG. 10, as in FIG. 9, the sub-data unit SUB_DU may bedistributed and written to pages included in one or more memory areas inthe memory device 110. A CID of a target command corresponding to thesub-data unit SUB_DU and a size value SIZE of the sub-data unit SUB_DUmay be written to each of the pages in which the distributed sub-dataunit SUB_DU is stored.

The CID of the target command corresponding to the sub-data unit SUB_DUand the size value SIZE of the sub-data unit SUB_DU may be written to aspare area SPARE_AREA.

The spare area is an area where meta information for a page (e.g., alogical address corresponding to a physical address of the page) isstored. The spare area may be a specific page included in a memoryblock, or may be positioned in each of the plurality of pages in whichthe distributed sub-data unit SUB_DU is stored, as illustrated in FIG.10.

Above, an operation of writing target data to the memory device 110 inthe memory system 100 is described.

Below, an operation of the memory system 100 to write a data unit fortarget data to the memory device 110 in order to maintain atomicity ofthe data unit in a recovery operation after the occurrence of an SPO isdescribed.

FIG. 11 is a diagram illustrating an SPOR (sudden power-off recovery)operation in the memory system 100 in accordance with an embodiment ofthe disclosure.

If an SPO (sudden power-off) occurs while the memory controller 120 ofthe memory system 100 writes data to the memory device 110, the memorycontroller 120 may perform an SPOR (sudden power-off recovery) operationupon rebooting after the SPO, to restore the memory device 110.

In the SPOR operation, the memory controller 120 should update mapinformation for data being written to the memory device 110 when the SPOoccurs. Updating map information for data means that the map informationfor the corresponding data is written to the memory device 110 and iscached in a map cache in the memory controller 120.

This is because, if the SPO occurs, the map information for the databeing written to the memory device 110 may be lost without being writtento the memory device 110.

Therefore, by scanning the memory device 110, the memory controller 120updates map information for a sub-data unit SUB_DU that was beingwritten to the memory device 110 at the time of the SPO, among sub-dataunits SUB_DU of the first data unit DU_1.

When updating the map information, the memory controller 120 may write alogical address corresponding to the physical address of a page to thespare area described above with reference to FIG. 10.

However, when an uncorrectable ECC (UECC) occurs in part, i.e., a piece,of the sub-data unit SUB_DU written to a plurality of memory areas dueto the SPO, map information for the sub-data unit SUB_DU should not beupdated. This is because the UECC in that piece of the sub-data unitSUB_DU means that writing of the sub-data unit SUB_DU has failed as aresult of the SPO.

In this case, in order to keep the atomicity of the first data unit, thememory controller 120 should unmap all the sub-data units SUB_DU for thefirst data unit DU_1. Unmapping data means that map information of thedata is rolled back to a state before the data is written. Thus, if datais unmapped, the data is no longer read.

That is to say, the memory controller 120 should roll back, during theSPOR operation, map information for all the sub-data units SUB_DU forthe first data unit DU_1 so that the entire first data unit returns to astate in which none of it is written to the memory device 110.

A detailed operation in which the memory controller 120 unmaps allsub-data units for a first data unit is described with reference toFIGS. 12 to 14.

FIGS. 12 to 14 are diagrams illustrating an operation when a UECC isdetected during the SPOR operation in the memory system 100 inaccordance with an embodiment of the disclosure.

First, it is assumed that a UECC is detected in a first sub-data unitSUB_DU_1, among sub-data units for a first data unit, written to thememory device 110. Further, it is assumed that the first sub-data unitSUB_DU_1 is written by a first sub-core SC_1 among the plurality ofsub-cores SC.

In FIG. 12, when the UECC is detected in the first sub-data unitSUB_DU_1, the first sub-core SC_1 may read a CID of a target command,which is stored together with the first sub-data unit SUB_DU_1, from atarget memory area where the first sub-data unit SUB_DU_1 is stored.

In FIG. 13, the first sub-core SC_1 may report the CID of the targetcommand read from the target memory area to the main core MC.

The main core MC instructs, based on the reported CID of the targetcommand, a second sub-core SC_2 to unmap a second sub-data unitSUB_DU_2, which is written to a memory area controlled by the secondsub-core SC_2, the first sub-data unit SUB_DU_1 and the second sub-dataunit SUB_DU_2 belonging to the first data unit DU_1.

To this end, the main core MC may provide the second sub-core SC_2 withthe reported CID. The second sub-core SC_2 may detect, based on thereported CID, a sub-data unit SUB_DU (e.g., the second sub-data unitSUB_DU_2) belonging to the first data unit DU_1 among data stored in thememory area controlled by the second sub-core SC_2.

The reason why, in this way, the first sub-core SC_1 reports the CID ofthe target command via the main core MC, instead of directly reportingthe CID of the target command to the second sub-core SC_2, is becausethe respective sub-cores SC independently operate without communicatingwith one another as described above.

In FIG. 14, the second sub-core SC_2 unmaps the detected second sub-dataunit SUB_DU_2 written to the memory area controlled by the secondsub-core SC_2.

The content described above with reference to FIGS. 11 to 14 isdescribed below using a flow chart with reference to FIG. 15.

FIG. 15 is a flow chart to assist in the explanation of the SPORoperation in the memory system 100 in accordance with an embodiment ofthe disclosure.

By way of example, the SPOR operation is executed by the memorycontroller 120 of the memory system 100.

First, the memory controller 120 detects the first sub-data unit of thefirst data unit while scanning the memory areas in the memory device 110(S1510).

The memory controller 120 performs an error check for the first sub-dataunit detected at the step S1510 (S1520), and thereby, determines whethera UECC has occurred in the first sub-data unit (S1530).

When a UECC has occurred in the first sub-data unit (S1530—Y), the firstsub-core, among the plurality of sub-cores in the memory controller 120,reports the CID of the target command to the main core (S1540).

The main core in the memory controller 120 transfers the reported CID toa different sub-core than the first sub-core, i.e., the second sub-core(S1550).

The second sub-core in the memory controller 120 detects, based on thereported CID, a second sub-data unit of the first data unit and unmapsthe detected second sub-data unit (S1560). Then, the process proceeds tothe step S1510. The second sub-data may be stored in the memory areacontrolled by the second sub-core.

On the other hand, when a UECC has not occurred in the icy firstsub-data unit (S1530—N), the process returns to the step S1510.

FIG. 16 is a flow chart to assist in the explanation of a method foroperating the memory controller 120 in accordance with an embodiment ofthe disclosure.

The memory controller 120 includes one main core and a plurality ofsub-cores which communicate with the main core and control data writeoperations for one or more memory areas among a plurality of memoryareas in the memory device 110.

First, the operating method of the memory controller 120 may includereceiving, by the main core, a target command for an operation ofwriting target data to the memory device 110, from the host (S1610).

Further, the operating method of the memory controller 120 may includedividing the target data into data units each having a size equal to orless than a threshold size and allocating the data units to theplurality of sub-cores, by the main core (S1620).

Lastly, the operating method of the memory controller 120 may includecontrolling the plurality of sub-cores in the memory controller 120 towrite a first data unit among a plurality of data units to the memorydevice 110 while maintaining atomicity of the first data unit (S1630).

The above-described operation of the memory controller 120 may becontrolled by the control circuit 123, and may be performed in such amanner that the processor 124 executes (drives) icy firmware in whichgeneral operations of the memory controller 120 are programmed.

FIG. 17 is a diagram illustrating a configuration of a computing system1700 in accordance with an embodiment of the disclosure.

Referring to FIG. 17, the computing system 1700 may include a memorysystem 100, a central processing unit (CPU) 1710 for controlling generaloperations of the computing system 1700, a RAM 1720 for storing data andinformation related with operations of the computing system 1700, aUI/UX (user interface/user experience) module 1730 for providing a userenvironment, a communication module 1740 for communicating with anexternal device in a wired and/or wireless manner and a power managementmodule 1750 for managing power used by the computing system 1700, whichare electrically coupled to a system bus 1760.

The computing system 1700 may include a PC (personal computer), a mobileterminal such as a smartphone or a tablet, or any of various otherelectronic devices.

The computing system 1700 may further include a battery for supplying anoperating voltage, and may further include an application chipset, agraphic-related module, a camera image processor (CIS), and a DRAM. Asthose skilled in the art can appreciate, the computing system 1700 mayinclude other components.

The memory system 100 may be of various types including a type whichstores data in a magnetic disk, such as a hard disk drive (HDD), and atype which stores data in a nonvolatile memory, such as a solid statedrive (SDD), a universal flash storage (UFS) device or an embedded MMC(eMMC) device. The nonvolatile memory may include a ROM (read onlymemory), a PROM (programmable ROM), an EPROM (electrically programmableROM), an EEPROM (electrically erasable and programmable ROM), a flashmemory, a PRAM (phase-change RAM), an MRAM (magnetic RAM), an RRAM(resistive RAM), and/or an FRAM (ferroelectric RAM). In addition, thememory system 100 may be realized as any of various types of storagedevices, and may be mounted in various electronic devices.

Although various embodiments of the disclosure have been illustrated anddescribed, those skilled in the art will appreciate that variousmodifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the invention. Therefore, thedisclosed embodiments are to be considered in a descriptive sense only,not for limiting the scope of the invention. The present inventionencompasses all variations and modifications of any disclosed embodimentthat fall within the scope of the claims including their equivalents.

What is claimed is:
 1. A memory system comprising: a memory device including a plurality of memory areas; and a memory controller configured to control the memory device, wherein the memory controller includes one main core and a plurality of sub-cores which communicate with the main core and control write operations on one or more memory areas among the plurality of memory areas, wherein, in response to a target command which instructs an operation of writing target data to the memory device, the main core divides the target data into data units each having a size equal to or less than a threshold size and allocates the data units to the plurality of sub-cores, and wherein the plurality of sub-cores stores a first data unit among the data units into corresponding memory areas such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device.
 2. The memory system according to claim 1, wherein each of the plurality of sub-cores independently controls write operations on the corresponding memory areas.
 3. The memory system according to claim 1, wherein the main core divides the first data unit into a plurality of sub-data units and distributes the sub-data units, and wherein the sub-cores write the distributed sub-data data units to the corresponding memory areas.
 4. The memory system according to claim 3, wherein a first sub-core among the plurality of sub-cores writes a first sub-data unit among the plurality of sub-data units to the corresponding memory area which is controlled by the first sub-core.
 5. The memory system according to claim 4, wherein, when writing the first sub-data unit to the target memory area, the first sub-core writes an identification of the target command and a size value of the first sub-data unit.
 6. The memory system according to claim 5, wherein the identification of the target command and the size value of the first sub-data unit are written to each of a plurality of pages to which the first sub-data unit is written.
 7. The memory system according to claim 6, wherein the identification of the target command and the size value of the first sub-data unit are written to a spare area where meta information for each of the plurality of pages is stored.
 8. The memory system according to claim 4, wherein the first sub-core reports the identification of the target command to the main core when an uncorrectable error is detected in a piece of the first sub-data unit during a sudden power-off recovery (SPQR) operation.
 9. The memory system according to claim 8, wherein the main core instructs, based on the identification of the target command, a second sub-core, different from the first sub-core among the plurality of sub-cores, to unmap a second sub-data unit which is written to the corresponding memory area controlled by the second sub-core among the plurality of sub-data units.
 10. A memory controller comprising: a memory interface configured to communicate with a memory device including a plurality of memory areas; and a control circuit configured to control the memory device, wherein the control circuit includes one main core and a plurality of sub-cores which communicate with the main core and control write operations on one or more memory areas among the plurality of memory areas, wherein, in response to a target command for an operation of writing target data to the memory device, the main core divides the target data into data units each having a size equal to or less than a threshold size and allocates the data units to the plurality of sub-cores, and wherein the control circuit controls a first data unit among the data units such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device.
 11. The memory controller according to claim 10, wherein each of the plurality of sub-cores independently controls write operations on different memory areas.
 12. The memory controller according to claim 10, wherein the main core divides the first data unit into a plurality of sub-data units and distributes the sub-data units, and wherein the sub-cores write the distributed sub-data data units to the corresponding memory areas.
 13. The memory controller according to claim 12, wherein a first sub-core among the plurality of sub-cores writes a first sub-data unit among the plurality of sub-data units to a target memory area which is controlled by the first sub-core.
 14. The memory controller according to claim 13, wherein, when writing the first sub-data unit to the target memory area, the first sub-core writes an identification of the target command and a size value of the first sub-data unit.
 15. The memory controller according to claim 14, wherein the identification of the target command and the size value of the first sub-data unit are written to each of a plurality of pages to which the first sub-data unit is written.
 16. The memory controller according to claim 15, wherein the identification of the target command and the size value of the first icy sub-data unit are written to a spare area where meta information for each of the plurality of pages is stored.
 17. The memory controller according to claim 13, wherein the first sub-core reports the identification of the target command to the main core when an uncorrectable error is detected in a piece of the first sub-data unit during a sudden power-off recovery (SPOR) operation.
 18. The memory controller according to claim 17, wherein the main core instructs, based on the identification of the target command, a second sub-core different from the first sub-core among the plurality of sub-cores to unmap a second sub-data unit which is written to a memory area controlled by the second sub-core among the plurality of sub-data units.
 19. A method for operating a memory controller including one main core and a plurality of sub-cores which communicate with the main core and control data write operations on one or more memory areas among a plurality of memory areas, the method comprising: receiving, by the main core, a target command from a host for an operation of writing target data to a memory device; dividing, by the main core, the target data into data units each having a size equal to or less than a threshold size and allocating, by icy the main core, the data units to the plurality of sub-cores; and controlling, by the sub-cores, a first data unit among the data units such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. 